Embodiments relate to a semiconductor device, and more particularly to a semiconductor device including a pad unit.
Generally, most of high-integrated semiconductor devices has been formed by stacking conductive layers (for example, a metal layer and an insulation film), and has been manufactured by interconnecting upper and lower conductive layers.
With the increasing precision and complexity of manufactured products, the number of stacked conductive layers increases in proportion to the increasing precision and complexity. If the number of stacking and patterning processes increases, the number of conductive layers accordingly increases. Thus, a bonding pad having a multi-layered conductive film may be used. Accordingly, many solutions for solving the problems encountered by stacked conductive layers formed in the semiconductor integrated circuit (IC) have been proposed. However, still many issues related to a bonding pad formed of a multi-layered conductive layer and related to a probe pad.
FIG. 1(i) is a plan view illustrating the semiconductor device, and FIG. 1(ii) is a cross-sectional view illustrating the semiconductor device taken along the line X-X′ of FIG. 1(i).
Referring to FIG. 1(i), the semiconductor device includes a metal pad 22, an adjacent circuit line 20 spaced apart from the metal pad 22, and an insulation film 26 configured to cover the adjacent circuit line 20 and one side of the metal pad 22. In this case, the insulation film 26 is partially etched to interconnect the metal pad 22 and the probe so that a fuse-open region 30 is defined. A defective or faulty semiconductor device caused by misalignment of the fuse-open region will hereinafter be described with reference to FIG. 1(ii).
Referring to FIG. 1(ii), the semiconductor device includes an interlayer insulation film 12 formed over a semiconductor substrate 10, a metal line 14 formed over the interlayer insulation film 12, an interlayer insulation film 16 formed over the metal line 14, a contact plug 18 formed over the metal line 14 to pass through the interlayer insulation film 16, a circuit line 20 formed over the interlayer insulation film 16, a metal pad 22 formed over the interlayer insulation film 16 so as to be coupled to a contact plug 18, an insulation film 24 formed over the circuit line 20 and the metal pad 22, and a Polymide Isoindro Quirazorindione (PIQ) layer formed over the insulation film 24. For connection to the probe, the metal pad 22 is exposed by etching the PIQ layer 26 and the insulation film 24. Here, a region formed by the exposed metal pad 22 is referred to as a fuse-open region 30.
When the probe is coupled to the fuse-open region 30, defective products may occur due to an insufficient process margin. For example, since the probe pin is configured to press the edge of the pad open region 30 or some parts of the PIQ layer 26, stress is applied to the fuse-open region, causing defects to products.
Stress is generated not only along an interface between the PIQ layer 26 and the insulation film 24 but also along an interface between the insulation film 24 and the metal pad 22. For example, there may arise a defective part (A) formed when the PIQ layer 26 comes off from the insulation film 24 may occur, and there may arise a defective part (B) causing a crack due to stress applied to an edge of the metal pad 22. In this case, the generated crack is transferred to the interlayer insulation film 16 formed below the metal pad 22, such that there may arise a defective part (C) caused when the interlayer insulation film 16 comes off from the lower metal line 14, resulting in a crack caused by an adjacent circuit line 20. In this case, since ions move from the metal line 14 along the crack, the metal pad 22 may be short-circuited to the circuit line 20.